some advice needed...

It is not really clear what kind of performance that you are refering to.

Are you refering to the study of the influence of e.g. max operation speed to external influences such as temperature, changes in supply voltage etc...

On silicon chips, the maximum operating speed is often evaluated by using ring oscillators. Here an odd number of invertors is put in cascade and fed back from output to input.

The loop delay time is than simply the inverse of the oscillation frequency.

The delay in a single invertor is determined by the loop delay time divided by the amount of invertors in the loop.

If you use enough invertors in the loop, you can get the oscillation frequency sufficiently low, such that you can measure it with other logic in the FPGA.

Making such a ring-oscillator should not be done in the usual way, as the whole chain would be optimized to a single inversion. You have to KEEP the original specified logic. You would also have to specifiy the placement and routing of individual invertors on the FPGA layout. This in order to control the interconnect delay.