SOLUTIONS??Laboratory Exercise 5 Timers and Real-time Clock

I've been studying the code for this exercise, but I erorr

code;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity counter is

generic (

n : integer := 4;

k : integer := 8

);

port

(

clock : in STD_LOGIC;

reset_n : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR(n-1 downto 0);

SW: in std_logic_vector(7 downto 0);

KEY : in std_logic_vector(1 downto 0);

LEDR : out std_logic_vector(7 downto 0)

);

end counter;

architecture rtl of counter is

signal Q_int: std_logic_vector(n-1 downto 0);

begin

PROCESS(clock, reset_n)

begin

if (reset_n = '0') then

Q_int<= (others => '0');

elsif ((clock'event) and (clock = '1')) then

if Q_int>= k-1 then

Q_int<= (others => '0');

else

Q_int <= Q_int + 1;

end if;

end if;

end process;

Q <= Q_int;

end rtl;

architecture Behavioral of counter is

component counter

generic

(

n : integer := 4;

k : integer := 8

);

end component;

begin

eight_bit: counter

generic map ( n => 8, k => 4)

port map eight_bit( clock, reset_n, Q, KEY(1), KEY(0), LEDR );

end Behavioral;