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Altera_Forum
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12 years ago

Sof file doesn't work

Hi, I'm working with Quartus II, using a Cyclone III device with a EPCS64 flash memory.

I've inherited of a Quartus project, I have a sof file of 2412 Ko called top_fpga_opg_master.sof

of type EP3C80.

I want to regenerate this sof file it without modificate my Quartus project at first ; so in Assignments I chose in

Device Family Cyclone III, in Target device -> specific device selected in 'Available devices' list

EP3C80F484I7 (because this is what is written in the first line of the sof file), and in Device and Pin Options

see the following attachment.

When I run assembler I've a new top_fpga_opg_master.sof with a size of 2412 Ko, so it's Ok !

But this new one doesn't work, so I don't know if I forgot to check an option or something else ?

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Did you check if Quartus compilation results in any critical warning or if large parts of logic are trimmed because of any error or missing connections?

    Did you inherited the hdl code or the complete Quartus project? I guess you have only hdl sources and included them in a new Quartus project, otherwise you would not need to select the device after peeking into sof file. Then you need exactly the same original settings in order to generate a fpga configuration operating in the same way. Please note that the same settings don't imply generating a sof file matching the old one: even if you will get the same behaviour, the new sof file will be always different from the previous one.

    I'd suggest you start by checking your project settings and enabling some optimization options, in particular 'timing driven synthesis'.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Yes I've inherited the complete Quartus project and don't have any critical warnings when I'm compiling

    or large parts of logic trimmed because of any error or missing connections.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Sorry maybe I look stupid but I don't know where to find 'timing driven synthesis' in settings ?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Does configuration complete correctly? Have conf_done and /status pins switched to the correct levels?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    In reality this is the first time I use Quartus II, and I don't know how to check all what you said above.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Critical Warning: Ignored Power-Up Level option on the following registers

    I have this critical warning just when starting Ananlysis & Synthesis.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Critical Warning: No exact pin location assignment(s) for 222 pins of 222 total pins

    When run Fitter
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You have to place the pins to exact output pins by using Assignments -> Pin Planner.

    But be exact with the Pins and with the I/O Standard and the Current Strength, maybe you also have to set some input/output Termination...