Sof file doesn't work

Did you check if Quartus compilation results in any critical warning or if large parts of logic are trimmed because of any error or missing connections?

Did you inherited the hdl code or the complete Quartus project? I guess you have only hdl sources and included them in a new Quartus project, otherwise you would not need to select the device after peeking into sof file. Then you need exactly the same original settings in order to generate a fpga configuration operating in the same way. Please note that the same settings don't imply generating a sof file matching the old one: even if you will get the same behaviour, the new sof file will be always different from the previous one.

I'd suggest you start by checking your project settings and enabling some optimization options, in particular 'timing driven synthesis'.