SOC priority rule question

Hello,

I have a question regarding SOC rules and their priorities.

I use on my design a double clocked memory block.

The logic runs at clock1x = 100 Mhz and the memory block uses clock2x = 200 Mhz.

Both clocks are syncron.

The 1 write port to the memory block accept writes on the fast clock, e.g. two writes per cycle from the slow clock domain.

Let for this example call them wp1_data_d, and wp2_data_d they are both clocked on clkc1x.

The registered memory latch runs on the fast clock2x.

The logic creating the wp1_data_d is short and has no problem to reach the 200Mhz clock

The logic creating the wp2_data_d is more and can only reach the 100 MHz clock.

Per default Timequest assumes that both have 1 cycle time to the memory_register.

I would like to set multicycle 2 for the wp2_data_d.

What is the correct way to set this?

Would this term be correct:

set_multicycle -setup -end -through [get_pins {mydesign|wp2_data_d*}] -to [get_clocks {pll|clock2x}] 2

set_multicycle -hold -end -through [get_pins {mydesign|wp2_data_d*}] -to [get_clocks {pll|clock2x}] 1

What happens if I would say it the other way around and give ALL signal form clkc1x to clck2x 2 cycle time

and would like to only give the signal which only have 1 cycle an exception rule?

Could I write the SDC file also that per default I give this rule:

set_multicycle -setup -end -from [get_clocks {pll|clock1x] -to [get_clocks {pll|clock2x}] 2

set_multicycle -setup -end -through [get_pins {mydesign|wp1_data_d*}] -to [get_clocks {pll|clock2x}] 1

Here both rules overlap, Would this work?Many thanks in in advance