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Altera_Forum
Honored Contributor
Honored ContributorSingle Clock vs Multiple Clock
Hi all,
I have a question about the clock signals. Say if I have a large scale of a network, where each node in the network is doing some operations. What if I use multiple clock signals, which all the clock is operating at same clock rate, to control the network. Each clock control some of the network nodes. Is this way can reach higher clock rate than using one single clock to control everything?6 Replies
Altera_ForumIn what context? Inside a single FPGA or across an entire system?
- Altera_Forum
Thanks for the reply.
I generate my network on a single FPGA. - Altera_Forum
Then using a single click across the whole chip is the most optimal solution. This is not always possible, but it is best to keep as much as possible in a single click domain.
- Altera_Forum
Thanks for the instruction.
I have another question about the fitting. When I check the failing path of this network, it seems that there is many failing path within one specific node. But there are many other nodes with same/similar structure, I am guessing it may be because the placement of that node is divided into different place on the chip ( I do not know how to check that). Is there any way I can check for the placement on the FPGA for each entity? Many thanks. - Altera_Forum--- Quote Start --- Thanks for the instruction. I have another question about the fitting. When I check the failing path of this network, it seems that there is many failing path within one specific node. But there are many other nodes with same/similar structure, I am guessing it may be because the placement of that node is divided into different place on the chip ( I do not know how to check that). Is there any way I can check for the placement on the FPGA for each entity? Many thanks. --- Quote End --- And if yes, is there any thing i can do to manage that?
- Altera_Forum
If you have failing paths, the easiest way to fix it is to improve pipelining in the code. These probably occur from to much logic between registers
