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Altera_Forum
Honored Contributor
Honored ContributorSingle Clock vs Multiple Clock
Hi all, I have a question about the clock signals. Say if I have a large scale of a network, where each node in the network is doing some operations. What if I use multiple clock signals, which...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Thanks for the instruction. I have another question about the fitting. When I check the failing path of this network, it seems that there is many failing path within one specific node. But there are many other nodes with same/similar structure, I am guessing it may be because the placement of that node is divided into different place on the chip ( I do not know how to check that). Is there any way I can check for the placement on the FPGA for each entity? Many thanks. --- Quote End --- And if yes, is there any thing i can do to manage that?
