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Altera_Forum
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18 years ago

Simulator: Can't find corresponding node name...

Hello, I have problems in the simulator of Quartus. I designed a VHDL-Code with SIGNALs and so on and made symbol file of this, for a schematic. In simulation I get the warning for differe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

First I set the attribute: 

SIGNAL memory_data:  STD_LOGIC_VECTOR(7 DOWNTO 0);
...
attribute preserve:	boolean;
attribute preserve of memory_data: signal is true;

than I set the option in the Assignment Editor:

http://img255.imageshack.us/img255/2327/simupreservedd1.gif (http://img255.imageshack.us/img255/2327/simupreservedd1.gif)

but it also doesn't work.

The signal I first tried to prevent from syntheziesing away was "io...." (see post befor). Now I changed my VHDL code and now the signal ist of the Type "Registered" and can be used for simulation without beeing synthezied away.

What could be another reason, that a signal is syntheziesed away?