New ContributorSimulation Waveform editor difference between input and combinational clock and other questions
Hello!
I'm trying to learn about timing analyses and simulation using Quartus Prime lite.
To do so I'm using the following simple design:
module Test01 (input clk, input e0, input e1, output reg q);
reg d1; /* synthesis preserve */
reg d2; /* synthesis preserve */
always @ ( posedge (clk))// source register
d1 <= e0;
always @ ( posedge (clk))// source register
d2 <= d1 & e1;
always @ ( posedge (clk)) // destination register
q <= d2 & 1'b1;
endmodule
The RTL view of the design looks like this:
In Quartus prime lite 17.1 I then use the Waveform Editor tool:
File->New->University Program VWF.
Inputs e0 and e1 is set to logic 1.
Input clk is set to a clock waveform of period 10ns.
Here are the results of the timing simulation done when choosing
Simulation->Run Timing Simulation
The signals used where selected by choosing:
Edit->insert->Insert Node or bus -> node finder
then, Filter: Post-synthesis, List, then select all signals.
The signals are of 4 categories:
input, output, registered, combinational.
I have a few questions to the simulation result:
Let us start with these two:
1) What is the difference between:
clk of type in and clk~input of type combinational?
2) What is the difference between:
q of type output and q~output of type combinational?
PS! If anyone else likes to run the design or some variation of it and have questions about timing analysis and simulation please feel free to post them in this thread. I guess a lot of beginners will have problems with these two topics.
