New Contributor
New ContributorI agree that the delay from latch edge of clock to data on register q-pin seems long.
However, since I'm new to this I have nothing to compare with, What should I expect?
What can I do to reduce the delay?
Included image is of the setup slack analysis for the path between register d1 - d2.
It seems that it is the arrival of the latch edge of the clock which is the main reason for the long delay.
The clock is connected to a clock pin on the FPGA.
The other inputs and outputs are connected to nearby pins.
ContributorI can be of little help, I don't know Cyclone10, I don't plan to use. I was happy with MaxII MaxV, Cyclone 2 3 4 5 but MAX 10 this time is driving me crazy.
I am not a beginner but timing closure on this tool seems not so simple and not deterministic.
Try start from there:
https://fpgawiki.intel.com/wiki/Timing_Constraints
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_tq_tutorial.pdf
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf
For timing closure analysys, I suggest follow competitor course, more aggressive and clear about topics. Intel new class where just slide. (Try a lesson, maybe I am not incline to slide video lesson instead of reading a good manual.)
Best site is this one from a consultant expert, start from bebinner then raise your level up, is clean and is forever one of my references:
