Forum Discussion
Altera_Forum
Honored Contributor
9 years agoUsing the VHDL file, this was my code:
module Question1 (x1, x2, f); input x1,x2; output f; assign f= (x1 & ~x2)|(~x1 & x2); endmodule **I compiled it** Then i used a vector waveform file, imported the nodes, set my end time. I then went on to Assignment> settings> simulator settings then changed simulation mode to functional. Then I generated a functional Simulation netlist. Then i click start simulation and the report window doesnt load, Quartus just crashes.