simulation problems

Thank you very much Brad. You've actually answered my question with your comprehensive post.

"When you think you have zero delay for "simple logic gates" but nonzero delay for a latch, could you just be zoomed out far enough that you don't see the small delay for the logic gates? You mention timescales in microseconds. If you are zoomed out far enough to see multiple microseconds, then the nonzero delay through each LUT/macrocell will look like zero. Zoom in enough so that you can see what is happening at the scale of nanoseconds."

This paragraph details on how to hide the propagation delay in a timing simulation, so I don't have to go to functional.

This is what I was talking about.

Also thank you very much for your insight as well on the using of latches and other info. I wouldn't have known this. Definitely made me stronger in knowledge about CPLDs and latches.

I will definitely read that guide.