Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

simulation problems

Ok this is really beginning to really tick me off. I am losing patience with quartus 2. Here is why: This may have to do with my ignorance. Whenever I create a simulation of lets say somet...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thank you for your input.

Basically in the timing simulation I want to eliminate the simulated propagation delay. So that the waveforms of the output and input are in-line.

A tutorial suggests that I put the end time to 100 micro seconds and the count every timing to 10.24 micro seconds which works for simple logic gates. I want to know if there is a real method in doing this.