simulation problems

I don't know whether your simulation issue is a matter of whether you are doing the simulation correctly (for example, doing functional simulation versus timing simulation to get what you are looking for). However, there are issues with latches in particular that might affect simulation of them.

Latches or any other combinational feedback loop are strongly discouraged in FPGA and CPLD designs. The timing analysis of combinational feedback loops creates special challenges for both the Fitter and Classic Timing Analyzer. (I don't know whether TimeQuest added a more PrimeTime-like analysis for this.)

I realize that you might be using latches in a Quartus design because you were told to for your class, but for real designs use latches only if there is not a good synchronous-design solution.

If you do use latches, carefully read Quartus handbook Volume 1, Section II, Chapter 6: Recommended HDL Coding Styles. Look at the section "Coding Guidelines for Registers and Latches --> Latches".