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DProk1
New Contributor
New ContributorSimulation problem of the PLL (27Mhz clock to 100Mhz clock)
Hi, I use Cyclone V 5CEBA2F17A7. the program I use is Quartus 17.1. I have problem with setting a PLL (27Mhz clock to 100Mhz clock). When I simulate the pll, I see gaps on the output clock (100Mh...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
May I know what exactly Gap is meaning, do you use model sim for simulation
DProk1New Contributor
New ContributorI use Qeustasim...
you can see the gaps in the file that I added to the qeustion above.
it is in pic No.3 in the file.
