Simulation problem of the PLL (27Mhz clock to 100Mhz clock)

Hi, I use Cyclone V 5CEBA2F17A7. the program I use is Quartus 17.1. I have problem with setting a PLL (27Mhz clock to 100Mhz clock). When I simulate the pll, I see gaps on the output clock (100Mh...