Simulation problem of the PLL (27Mhz clock to 100Mhz clock)

Hi,

I use Cyclone V 5CEBA2F17A7.

the program I use is Quartus 17.1.

I have problem with setting a PLL (27Mhz clock to 100Mhz clock).

When I simulate the pll, I see gaps on the output clock (100Mhz).

settings:

input clock 27Mhz.

Output clock 100Mhz.

The setting of the pll are seen on the attached file (pic 1 and pic 2).

The simulation is in pic 3.

why there are gaps on the simulation and how do I fix this issue?

thank you