simulation performance

It's too bad that the functional simulation wasn't fast enough for you, but the absence of glitches in that simulation mode makes sense. The glitches you see in timing mode are probably dependent on propagation delays through combinational logic. For an edge-sensitive signal like a logic-driven clock (which you shouldn't be using anyway), the glitches would of course be a design concern. For signals in synchronous paths, the glitches don't matter because the slack reported by static timing analysis tells you whether the glitches will settle out in time.