Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThank you very much indeed. But now I have another problem. I have designed my project in Block Diagram/Schematics. Now I want to simulate this in ModelSim. Do I have to convert every block into VHDL? If so, which VHDL file do I have to compile??? Do you take only the top_level design or every design file??? I really need help in this matter. Thanks.