Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Simulation of RAM 2 port megafunction

Hello, I am trying to simulate the RAM 2 port Mega function in Questasim tool, when i drive the inputs using write clock its going fine but when i try to read that same location am not getting ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

to me it looks like you're doing nothing wrong, but what bothers me is that there is a warning on each rising edge of rdclk (the yellow triangles on top of the waveforms), even at the end where none of the signals is 'X'. Therefore, can you please share the log produced by ModelSim?

Also, what is strange is that there is a sub_wire0 in your signals, which I would not have expected at the top level of your design (these sub_wire things typically only exist inside a MegaFunction, and are not supposed to be touched... well the old "unless you exactly know what you're doing").

Best regards,

GooCooCluster