Here is the complete error
# Loading work.pwm_main# Loading work.altufm_osc0_altufm_osc_1p3# ** Error: (vsim-3033) D:/documents and Settings/VALESN1/My Documents/Téléchargements/an501_design_example/AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example/quartus/pwm_main.v(78): Instantiation of 'maxii_ufm' failed. The design unit was not found.# Region: /pwm_main/u1# Searched libraries:#
D:\documents and Settings\VALESN1\My Documents\Téléchargements\an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\simulation\modelsim\rtl_work# Loading work.clk_gen# Loading work.duty_cycle# Loading work.pwm_gen# Error loading design
I thinf it is a problem with the simulation of the internal clock