Simulation in ModelSim Altera Starter Edition

Hi thepancake,

test benches are surely a good workaround and surely the most certain way to simulate a design, but sometimes one needs an opportunity for quick test without to have to write a new test bench. It is really a pity, that this feature is not implemented.

Apropos the test benches. I tried the following test bench with Quartus 9.1 SP2 :

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library ieee ;

use ieee.std_logic_1164.all;

use ieee.numeric_bit.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_textio.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

library lpm;

use lpm.lpm_components.all;

library altera;

use altera.altera_primitives_components.all;

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entity testbench_1 is

end testbench_1;

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architecture test_1 of testbench_1 is

signal d : std_logic_vector(3 downto 0);

signal q : std_logic_vector(1 downto 0);

begin

dut: entity work.mv78200(behv1)

port map(d, q);

stimulus : process is

begin

d(0) <= '0';

d(1) <= '0';

d(2) <= '0';

d(3) <= '0';

wait for 500ns;

d(0) <= '1';

d(1) <= '1';

d(2) <= '1';

d(3) <= '1';

wait;

end process stimulus;

end architecture test_1;

and I got again and again the error message:

error (10533): vhdl wait statement error at testbench_1.vhd(43): wait statement must contain condition clause with until keyword.

(Line 43 is the statement "wait for 500ns;")

With ModelSim Altera Edition I can use this test bench without any problems. Any ideas?