Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Simulation in ModelSim Altera Starter Edition

Hi guys, need a little bit help. I try ModelSim ALTERA STARTER EDITION 6.5b for the first time, have created a test project (two inputs, two outputs) and wanted to simulate it. My problem ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

A testbench is just an HDL text file with signals to drive your unit under test. Simply instantiate your UUT, and create some behavioural signals. for example, to generate a clock in VHDL, you can simply do this:

signal clk : std_logic := '0';

...

clk <= not clk after 10 ns; --100 MHz clock.

and for stimulus: 


process
begin
  input <= 0;
  wait for 100 ns;
  input <= 1;
  wait for 500 ns;
  input <= 2;
  for 1 in 1 to 20 loop
    wait until rising_edge(clk);
  end loop;
  input <= 3;
  wait;
end process;

This is just the tip of the iceburg