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Altera_Forum's avatar
Altera_Forum
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12 years ago

Simulation Freezing

I'm trying to simulate a code written in Verilog in Quartus using ModelSim but whenever it wants to simulate the code I see the whole software freezing. I tried reinstalling the software but it did not help. Does anyone know what could be the cause of this issue?

Thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Check your verilog.

    If you have a simulation loop with no time step, the simulator will get stuck trying to toggle the signals, with no increase in time.

    Some classic examples are a forever loop for clock that has no time delay in it, or a counter that has nothing that gates the counting once it starts. (IE it's in a always @ (*) block)

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Check your verilog.

    If you have a simulation loop with no time step, the simulator will get stuck trying to toggle the signals, with no increase in time.

    Some classic examples are a forever loop for clock that has no time delay in it, or a counter that has nothing that gates the counting once it starts. (IE it's in a always @ (*) block)

    Pete

    --- Quote End ---

    I am having the same issue, but I am designing it schematically. Any recommendations?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Do you have registers around all feedback paths like counters?

    That would be the classic example. if you have sum = sum + 1 type of logic, but no register in the path, it will cause the simulator to loop for ever.

    so sum_c = sum_r + 1 should work if sum_r is the registered version of sum_c. Now it will only step at the clock rate.

    Pete