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Altera_Forum's avatar
Altera_Forum
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15 years ago

Simulation fails when it goes into big design.

Ok guys, I have designed a small block that does some counting and put some signals to zero while its counting.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think that the synthesizer was a bit confused by the sensitivity list and didn't know how to synthesize your project.

Still it is strange that your design meets timing requirements and still fails in timing simulation... Are you sure that the inputs you use for your simulation follow the timing requirements that you gave? Do you have any unconstrained I/O paths?