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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Simulation fails when it goes into big design.

Ok guys, I have designed a small block that does some counting and put some signals to zero while its counting.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm surprised how Altera doesn't have any relevant complaints about the big design and its failing within the timing simulation.