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Altera_Forum's avatar
Altera_Forum
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15 years ago

Simulation fails when it goes into big design.

Ok guys, I have designed a small block that does some counting and put some signals to zero while its counting.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Oups sorry... I don't know why I thought that EVBCONDB was changing in the process...

If EVBCONDB is constant you can move the code that sets multiplier outside of the process.

How about CLK_OUT? Does it come from a pll, a clock input?