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Altera_Forum's avatar
Altera_Forum
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15 years ago

Simulation fails when it goes into big design.

Ok guys, I have designed a small block that does some counting and put some signals to zero while its counting.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Where does the clock CLK_OUT come from? Is it clean?

I think that you should remove EVBCONDB_reg from the sensitivity list and only leave the clock (and a reset input, if possible). You should update multiplier in the process under the line where you update EVBCONDB_reg.

I don't know how Quartus will synthesize this, but the simulator may execute several times the process after a rising edge of the clock, because of the changes in EVBCONDB_reg.