SImulation error

SW in use:

Quartus Prime 20.1.1

University Program VWF

AHDL file:

-- OUTPUT declarations

Dataout[][] = OUTPUT_LATCH_ff[][].q;

Data_OUT1[] = OUTPUT_LATCH_ff[0][].q;
Data_OUT2[] = OUTPUT_LATCH_ff[1][].q;
Data_OUT3[] = OUTPUT_LATCH_ff[2][].q;
Data_OUT4[] = OUTPUT_LATCH_ff[3][].q;

when the project is simulated the

Data_OUTX[] shows the correct waveform

Dataout[][] shows XX

any idea why the 2 dimensional bus is not simulating correctly??

best regards

Kurt