Forum Discussion
Kurtlin
New Contributor
New ContributorSImulation error
SW in use:
Quartus Prime 20.1.1
University Program VWF
AHDL file:
-- OUTPUT declarations
Dataout[][] = OUTPUT_LATCH_ff[][].q;
Data_OUT1[] = OUTPUT_LATCH_ff[0][].q; Data_OUT2[] = OUTP...
SyafieqS
Super Contributor
Super ContributorKurt,
May I know if there is any update regarding my previous request?
