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Kurtlin's avatar
Kurtlin
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4 years ago

SImulation error

SW in use: Quartus Prime 20.1.1 University Program VWF AHDL file: -- OUTPUT declarations Dataout[][] = OUTPUT_LATCH_ff[][].q; Data_OUT1[] = OUTPUT_LATCH_ff[0][].q; Data_OUT2[] = OUTP...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Kurt,


More information needed here. A snapshot of the error message and the simulation if possible?