simulation error

im a newbie in quartus II.i tried to simulate the full adder in verilog hdl but it seems cant work!!when i tried to compile the files, there's no error but have a few warnings.

but when it comes for simulation...the msg appeared>>

Error: Can't launch the Active-HDL software -- the path to the location of the executables for the Active-HDL software were not specified or the executables were not found at specified path.

Error: You can specify the path in the EDA Tool Options page of the Options dialog box or using the Tcl command set_user_option.

Error: NativeLink Simulation failed

Am i did the wrong files source code or the way i setting the eda simulation tools is not correct??pls help me...

this is my full adder file

module fulladder (a,b,carry_in,sum,carry_out);

input a,b;

input carry_in;

output [1:0] sum;

output carry_out;

half_adder H1 (carry, sum[0], a, b);

half_adder H2 (carry_out, sum[1], carry, carry_in);

endmodule

module half_adder(carry, sum, a, b);

input a;

input b;

output carry;

output sum;

xor X1 (sum, a, b);

and A1 (carry, a, b);

endmodule