Simulating mixed project blocks in Quartus/ModelSim

Good morning everyone,

I am new to Altera Quartus tool.

I have started a project using Quartus 15.1 and Cyclone IV for a target.

I have written some Verilog code which I successfully simulate in ModelSim and I am satisfied with the results.

At some points in my project I would like to include some of the hardware resources provided by the chip (such as hardware multiplier or pll).

To begin with, I have tried to use an internal PLL to increase the internal clock frequency, which should be quite straightforward to generate and simulate.

At this point I'm not sure how to proceed.

The documentation I have found mentions using megawizard configurator to include a PLL in the design. This will generate a file with the extension ".bdf"

I haven't been able to find out how to generate links between such a bdf file and the other hand-written Verilog files of my project.

I am equally unsure how I can get to simulate the whole thing in ModelSim.

An alternative would be to get a Verilog file to configure the PLL but the documentation I've seen so far doesn't really explain how to proceed.

Please forgive me if those questions are dumb or basic, if there is a section of the manual which explains all this, then I've failed to detect it, please just point it out and i'll study it.

Thanks in advance,

Henri.