Simulating Bidirectional IO

Consider this simple function whereby a bidirectional I/O bus is forced to a value of d255 or a hi-z state depending on the state of a select line;

module bidir_io

(

input select,

inout [7:0] io_bus

);

assign io_bus = (select? 8'd255 : 8'bz);

endmodule

When simulated in Quartus I get the result shown in the attachment. Two versions of io_bus appear, one gets labeled "result" and properly shows the value of d255 when select is asserted. The other remains in the hi-z state all the time. This is OK, except the "result" bus gets expanded into its 8 constituent bits and gobbles up space in the window. Also, if there are other signals in the design, "result" always ends up as the last waveform in the display, not a convenient spot. Any way to get "result" to converge to a single, 8 bit bus? Am I being picky?