Simulate with Altera IP in ModelSim

In principle you compile any source code into a chosen library which defaults to work. Then you simulate any level by selecting from work.

you will then need to add waveform file by choosing your inputs and applying logic.

Ideally a testbench can be used to inject data into top level.

When you compile, check what is the default library.

The nativelink is not a separate simulator but it launches modelsim from quartus (ready for your design), I never use it.

Many designers use tcl or do file to compile and run simulation at a single click.

If I am not mistaken you need the altera_mf library. For VHDL:

library altera_mf;
use altera_mf.altera_mf_components.all;

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In principle you compile any source code into a chosen library which defaults to work. Then you simulate any level by selecting from work.

you will then need to add waveform file by choosing your inputs and applying logic.

Ideally a testbench can be used to inject data into top level.

When you compile, check what is the default library.

The nativelink is not a separate simulator but it launches modelsim from quartus (ready for your design), I never use it.

Many designers use tcl or do file to compile and run simulation at a single click.

--- Quote End ---

Hi Kaz, I am not seeing an option to simulate all the files in the WORK library. the option is grayed out. so if i simulate just my top level entity file, i get an error saying it cannot find the instance of RAM. also if i select multiple files in the simulate option from the toolbar i am getting the same error. However for compile I was able to select multiple files like this and it compiled ok.

I dont have much experience with using tcl or do. I've only ever modified the waveform directly in quartus and run simulation. is there some resource that would help me understand how to use these different things?

create a text file and save with extension .tcl (or .do)

example:

---------------------------------

quit -sim

# compile into work

vlib ./work

vcom -93 -work work ../folder1/folder2/my_file.vhd

vcom -93 -work work ../folder1/folder2/my_top_tb.vhd

# simulate testbench architecture a, or any file

vsim -t ps work.my_top_tb(a)

do wave.do

radix dec

run -a

---------------------

to run it type in modelsim command window : do file_name.tcl

if you haven't waveform file you can start with an empty one, then after simulation add nodes to the waves.

You need to make sure you got altera libraries compiles and appear in modelsim list.

--- Quote Start ---

create a text file and save with extension .tcl (or .do)

example:

---------------------------------

quit -sim

# compile into work

vlib ./work

vcom -93 -work work ../folder1/folder2/my_file.vhd

vcom -93 -work work ../folder1/folder2/my_top_tb.vhd

# simulate testbench architecture a, or any file

vsim -t ps work.my_top_tb(a)

do wave.do

radix dec

run -a

---------------------

to run it type in modelsim command window : do file_name.tcl

if you haven't waveform file you can start with an empty one, then after simulation add nodes to the waves.

You need to make sure you got altera libraries compiles and appear in modelsim list.

--- Quote End ---

Hi Kaz, thank you! Actually just after posting my reply earlier, i was able to get it to simulate with all the files. on another forum, i found the vsim command, so i tried 'vsim -i top.vhd, ram.vhd' and it simulated successfully!

Then i tried adding signals from my object window to my wave and running the simulation. However, i am now getting an error saying it is unable to load my data initialization file.

" Fatal: (vsim-7) Failed to open VHDL file "ram_data.hex" in rb mode. "

Is there a way for me to load the memory from my MIF/HEX file for simulation purposes?

you can copy the hex file into modelsim folder.

Alternatively look at path of hex in ram file and you can edit it to point correctly from modesim level.

This a common problem of relative path of hex file as it is decided in quartus level (not modelsim level)