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Altera_Forum
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11 years ago

Simulate FIR MegaCore IP with Verilog in ModelSim

I am trying to simulate the FIR MegaCore IP with Verilog test bench in ModelSim Altera Starter Edition. I have generated the IP with Verilog as chosen language. Generated simulation files and sc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Your modelsim license supports one hdl (not mixed). so try generate all in vhdl or all in verilog (module and testbench)

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I am aware of that... I am generating the IP as Verilog! It's their fault of providing it in VHDL and the Top-Level in Verilog!

And then they say you are not allowed to compile mixed language projects... Are they kidding me?!!

I've designed the whole project in Verilog... it doesn't make sense to write it again in VHDL just for the sake of Altera!