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Altera_Forum
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11 years ago

Simulate FIR MegaCore IP with Verilog in ModelSim

I am trying to simulate the FIR MegaCore IP with Verilog test bench in ModelSim Altera Starter Edition. I have generated the IP with Verilog as chosen language. Generated simulation files and sc...
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Altera_Forum
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11 years ago

Your modelsim license supports one hdl (not mixed). so try generate all in vhdl or all in verilog (module and testbench)