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Altera_Forum
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14 years ago

Simplified Equation

Hello Folks, First time poster, I am using Altera Quartus 2 ver. 9.1. I have created a simple combinational logic circuit where the Boolean expression simplifies to a single input. ...
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Altera_Forum
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14 years ago

It's true, some Quartus features don't work for CPLD synthesis. But I still don't understand the exact problem. The logic can be minimized by pencil and paper method, so there' won't be doubts about the result. The implementation for Y = B should be clear without a floorplan, what are you missing?

You can however change the project to a FPGA target to evaluate logic minimization during synthesis.