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Altera_Forum
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12 years ago

Simple syntax error

I have no clue why quartus does not want to run this all in one module. I get this error: Error (10170): Verilog HDL syntax error at Verilog1.v(6) near text "begin"; expecting "endmodule"...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You have a semi-colon after the always statement

it should be: 


    module hex7disp(A, n, O, h);
       input A, n, O;
       output reg  h;
   
   
       always @ (A or n or O or h)
       begin
          if (A)
	    h <= 7'b0001000;
          else if (n)
	     h <= 7'b0101011;
          else if (O)
 	     h <= 7'b1000000;
          else
	     h <= 7'b0111111;
       end
    endmodule