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It's a sign extension. (Actually, it is zero-extension if the word is unsigned.) You need it because:
b) VHDL requires that assignments have the same length vectors on both sides of the <= (or := ), and
c) VHDL neither auto-extends operands nor truncates results to make the vector lengths match (unlike Verilog).
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are you sure? try multiply 8 bits value by 8 bits value onto 16 bits result
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As noted in this thread, it is better to use the resize() function (from numeric_std) on signed or unsigned types than to explicitly use the '0' & foo.
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why? what is the resize doing anyway?
Honored Contributor
