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Oppps, thanks kaz. it's late and I'm a bit tired. So actually it is working correctly. So why is the '0' in ('0' & cin) needed for?
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It's a sign extension. (Actually, it is zero-extension if the word is unsigned.) You need it because:
a) adding two
n-bit vectors gives you an
n+1-bit sum (a carry is generated),
b) VHDL requires that assignments have the same length vectors on both sides of the <= (or := ), and
c) VHDL neither auto-extends operands nor truncates results to make the vector lengths match (unlike Verilog).
As noted in this thread, it is better to use the resize() function (from numeric_std) on signed or unsigned types than to explicitly use the '0' & foo.
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