Simple Signed Adder is complex to understand

The std_logic_vector itself just means a bus of bits and so has no sign meaning.

The libraries like numeric_std then understands your intention. If you declared std_logic_vector then you can cast it (between brackets) as signed as I did and then it is treated as signed. If you don't it will issue error when adding as it does not understand your intention of bus (but this depends on libraries...)

Basically signed and unsigned are similar at addition/subtraction and it is only their interpretation by user is different. But for multiplication/division they differ in result.

And this why two's complement has been invented as addition/subtraction is same as unsigned.