Simple problem with clock generation

Hi there,

I am experiencing an apparently simple, but frustating problem: when I generate a clock signal with a process that shows an empty sensitivity list, modelsim simulation returns an undefined value for the logical level that has not been initialized. However, compilation runs without any error or warning. Here's the code:

library ieee;use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb_test is

end entity tb_test;

architecture tb of tb_test is

signal clk : std_logic;

constant clk_period : time := 10 ns;

begin

clk <= '1';

process

begin

wait for clk_period/2;

clk <= '0';

wait for clk_period/2;

clk <= '1';

end process;

end tb;

I will attach a picture to show the behaviour of the signal clk during simulation.

Thank you very much in advance for any hint.