Simple problem with clock generation

you first set clock outside the process to'1', then start assigning values inside the process. You now have multiple drivers on the same signal. What is the level if a line is both connected to '1' and '0'? And for '1' and '1'? This is what you see. The syntax is correct, so the compilation for simulation will pass, I think that, should you do a similar thing for synthesis you'll find you get a multiple driver error.