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Honored Contributorsimple Infinite loop expansion header using Altera DE2-70 Cyclon ii
I write a simple infinite loop to generate an output at expansion header. The reason is I want to generate a simple logic digital signal and probe it at MSO oscilloscope, in order to play around with triggering function etc in oscilloscope.
The problem is I got errors: Error (10106): Verilog HDL Loop error at testing2.v(22): loop must terminate within 5000 iterations Error (12153): Can't elaborate top-level user hierarchy Is the limit of iterations come from cyclon II or the software? For your information I use free Quartus II 12.1 Web Edition Software. How to solve it so that I can generate constant (infinite loop) digital signal from expansion header? I also notice that "assign GPIO_0[1] = A;" is not working when we try to use the operational function. Here is the code. I use the set_global_assignment preference for .qsf file. The .qsf work just fine.module testing2 (A,B,C,CLOCK_50,GPIO_0,GPIO_1);
output GPIO_0;
output GPIO_1;
output A;
output B;
output C;
input CLOCK_50;
reg A, B, C;
assign GPIO_0 = CLOCK_50;
assign GPIO_0 = A;
assign GPIO_0 = B;
assign GPIO_0 = C;
initial
while(1)
begin
A = 0;
B = 0;
C = 0;# 5
A = 1;
B = 0;
C = 0;# 5
A = 1;
B = 1;
C = 0;# 5
A = 1;
B = 1;
C = 1;# 5
A = 0;
B = 0;
C = 0;
end
endmodule 
