New ContributorSIMMULATION ERROR
I face a question to do the simulation. This is what i got from the simulation report.
I checked the file assignment.do but i cannot access. I deleted the novopt part in the simulation setting.
Determining the location of the ModelSim executable...
Using: C:\intelFPGA_lite\20.1\modelsim_ase\win32aloem
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off assignment2 -c assignment2 --vector_source="C:/Users/Lenovo/Downloads/des assignment/Waveform3.vwf" --testbench_file="C:/Users/Lenovo/Downloads/des assignment/simulation/qsim/Waveform3.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Tue Jan 07 09:26:14 2025
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off assignment2 -c assignment2 --vector_source="C:/Users/Lenovo/Downloads/des assignment/Waveform3.vwf" --testbench_file="C:/Users/Lenovo/Downloads/des assignment/simulation/qsim/Waveform3.vwf.vt"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Lenovo/Downloads/des assignment/simulation/qsim/" assignment2 -c assignment2
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Tue Jan 07 09:26:22 2025
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Lenovo/Downloads/des assignment/simulation/qsim/" assignment2 -c assignment2
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file assignment2.vo in folder "C:/Users/Lenovo/Downloads/des assignment/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4733 megabytes
Info: Processing ended: Tue Jan 07 09:26:24 2025
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Completed successfully.
**** Generating the ModelSim .do script ****
C:/Users/Lenovo/Downloads/des assignment/simulation/qsim/assignment2.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vsim -c -do assignment2.do
Reading pref.tcl
# 2020.1
# do assignment2.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 09:26:27 on Jan 07,2025
# vlog -work work assignment2.vo
# -- Compiling module assignment2
#
# Top level modules:
# assignment2
# End time: 09:26:27 on Jan 07,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 09:26:27 on Jan 07,2025
# vlog -work work Waveform3.vwf.vt
# -- Compiling module assignment2_vlg_vec_tst
#
# Top level modules:
# assignment2_vlg_vec_tst
# End time: 09:26:27 on Jan 07,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Executing ONERROR command at macro ./assignment2.do line 5
Error.
