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I don't see how the logic could be "changed" by run analysis. The closest connection between design and the signaltap block is a chain of pipeline registers clocked by the aquisition clock. There are additional registers for signals operating as trigger and a combinational LE for storage quailifiers, but nothing that would be packed with user logic by Quartus.
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Well, I would agree with you, that it shouldn't. Like your inside information suggested, it should not behave like what I have. However, true enough it is behaving this way, and somehow, it recovered, after I rebooted the machine(see my last post). Looks like something is really "wrong" with Signaltap and Quartus II 12.0sp2...and it is behaving beyond the "boundary" of the Signaltap developer.
Is there any improvement to Signaltap in 12.1sp1, in your opinion?
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