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I would think too it could be a cross talk problem with the JTAG signals, or maybe a power supply decoupling problem? For example on the Cyclone III and IV, the VCCA supplies are used for both the PLLs and the JTAG system, IIRC.
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There is of course such possibility, especially with Rysc's case. where another "external" interface may render the Jtag interface being "choked". However in my case, the internal PLL are all still stable and output a correct frequency. The ADPLL that I am referring to, is purely a logic design, purely LE, and got nothing to do with the PLL inside the cyclone. Even if the clock is de-stablised by the "JTAG noise", it should be able to recover, unless, the logic has been "changed" by the "Run Analysis".
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