Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi Daixiwen
I'm using Cyclone IV dev. kit. So the 125MHz clock should be stable. My design violates some of my timing constraints. (It's weird that 125MHz clock has negative slack in holding time even though I've added "create_clock -name {clk125M} -period 8.000 -waveform { 0.000 4.000 } [get_ports {clk125M}])." Does this negative slack cause me this problem?