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Altera_Forum
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9 years ago

SignalTap II issue

Hello, Here is debounce state machine: module debounce_explicit(input clk, reset, sw, output reg db_level, db_tick); //symbolic state declaration localparam zero = 2'b...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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Run "Report Ignored Constraints" command in TimeQuest to see if all your SDC commands are accepted.

After running "Report Unconstrained Paths" check which actual ports are unconstrained (In Report window see Unconstrained Paths -> Setup Analysis -> Unconstrained Input Ports or Unconstrained Output Ports). This way you will find out which ports are left unconstrained or there is some error in your SDC file.

I am guesing that you will find that those two input ports are altera_reserved_tdi and altera_reserved_tms. You can also use set_false_path for those ports. For JTAG i use:

create_clock -period "10 MHz" -name altera_reserved_tck [get_ports altera_reserved_tck]

set_false_path -from [get_ports {altera_reserved_tdi}]

set_false_path -from [get_ports {altera_reserved_tms}]

set_false_path -to [get_ports {altera_reserved_tdo}]

# Specify the JTAG clock in a group

set_clock_groups -asynchronous -group altera_reserved_tck

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Yes, it's the case, the unconstraiuned inputs are altera_reserved_tdi and altera_reserved_tms.

Concerning constraints for JTAG signals is it necessary to create altera reserved_clk, as it's already present ?

https://www.alteraforum.com/forum/attachment.php?attachmentid=13258

Thanks