Honored Contributor
Honored ContributorIt's been a while. I don't know where you are with this. Thinking that the JTAG Chain Debugger may not be that useful to detect possible signal integrity issue along the JTAG chain, I decided to write one myself. Brushing up my skill of TCL and learning a bit about TK, I finally got something done in a presentable state. Having had a couple of good weekends didn't help either;) After this experience, I am still not fond of TCL/TK at all. I wish one day this EDA industry can get away from it. You can read about and get the script from this page signaltapit.com/jtag-chain-tester/ I believe it is a better way to test JTAG chain.
Reading your last post, somehow, I think there is another possible suspect apart from JTAG communication. Have you paid attention to the timing on the acquisition clock domain? Do you have the correct timing constraints set on that clock domain and all timings are met?
